Electrical & Electronics
555 Timer Calculator
Calculate 555 oscillator timing and one-shot pulse width, or choose standard resistors for a target frequency or pulse.
Your inputs
Your results
- Frequency
- —
- Period
- —
- High time
- —
- Low time
- —
| Output high duty cycle | — |
|---|---|
| RA · Ideal resistance | — |
| RB · Ideal resistance | — |
| Target error | — |
| Duty-cycle error | — |
Normalized timing only. Actual output voltages depend on the timer and load.
f = 1 / (ln(2) × (RA + 2RB) × C)Calculate a 555 oscillator or one-shot pulse
Estimate timing for the standard astable or monostable 555 circuit shown by the tool. Astable operation repeats a high and low output; monostable operation produces one timed pulse after a trigger. Calculate from resistor values or search nearby preferred values for a timing target. The ideal model excludes component tolerances, leakage, trigger behavior and device-specific operating limits.
Step by step
- Choose astable or monostable operation and enter capacitance. In calculation mode, enter RA and, for astable operation, RB. Resistance fields default to kΩ and capacitance to nF.
- Review the timing results and diagram. Astable results include high time, low time, period, frequency and the percentage of the period spent high; monostable results show pulse width.
- To design toward a target, choose the resistor-finding mode and an E12, E24 or E96 series. Enter frequency and high-state duty cycle for astable operation, or pulse width for monostable operation, then compare the selected resistors and reported errors.
Settings and limits
- Timing equations
- Astable high time is ln(2) × (RA + RB) × C; low time is ln(2) × RB × C. Period is their sum and frequency its reciprocal. Monostable pulse width is ln(3) × RA × C. Using logarithms explains small differences from formulas with rounded timing constants.
- High-state duty cycle
- For the standard astable circuit with positive resistors, the high-state duty cycle is above 50% and below 100%. Design targets must lie strictly inside that range. Other circuits can produce different duty cycles, but they are outside this tool's model.
- Preferred resistor search
- The search compares nearby candidates from the selected series and balances frequency and duty-cycle errors for astable operation. It is a local search, not a guarantee of the best pair across every resistance. Reported duty error is in percentage points; component tolerance is not included.
Worked example
Select astable calculation with RA = 10 kΩ, RB = 10 kΩ and C = 100 nF. The capacitor charges through both resistors and discharges through RB, so high time is twice low time.
| RA | RB | C | tH | tL | T | f | Dhigh |
|---|---|---|---|---|---|---|---|
| 10 kΩ | 10 kΩ | 100 nF | 1.38629 ms | 0.693147 ms | 2.07944 ms | 480.898 Hz | 66.6667% |
High time is about 1.38629 ms and low time about 0.693147 ms, giving a 2.07944 ms period, 480.898 Hz frequency and 66.6667% high-state duty cycle. With the same RA and C in monostable mode, pulse width is about 1.09861 ms.
Questions and troubleshooting
Why is a 50% astable target rejected?
Equal high and low times would require zero RA in this particular ideal circuit. The tool requires positive resistors and accepts only targets inside the displayed range. Use another supported topology or a separate timing approach if equal high and low times are required.
Why do the selected resistors miss my target?
Preferred resistor values are discrete, and one pair must address both astable targets. Compare frequency error and duty error together. A denser resistor series or a different capacitor can change the available candidates; actual component tolerances add further variation.
Does the diagram cover everything needed for a physical circuit?
It illustrates the timing arrangement used in the equations. Check the actual timer's pinout, supply range, decoupling, trigger conditions and output limits in its documentation. The calculator does not validate those device-specific requirements.