Electrical & Electronics
BJT Amplifier & Emitter Follower Calculator
Calculate bias, loaded gain, resistance and signal swing for NPN/PNP amplifiers.
Your inputs
Your results
- IC
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- VCE
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- Voltage · Vout,DC
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- Voltage gain · Av,S
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- Voltage gain · Av,B
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- Resistance · Rin
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- Resistance · Rout
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- gm
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- rπ
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- Voltage · Vout,pk
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- Maximum · Vout,pk
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—Compare common-emitter gain with emitter-follower loading
Estimate midband small-signal gain after calculating DC bias. Compare common-emitter and emitter-follower stages, source loading and approximate clipping headroom. The model excludes frequency-dependent capacitors, transistor output resistance, noise and detailed distortion.
Step by step
- Choose transistor polarity, bias method and amplifier topology. Establish an active DC operating point before interpreting small-signal results.
- Enter AC load, source resistance, input peak and thermal voltage. For common-emitter mode, choose whether the emitter resistor is ideally bypassed.
- Compare source-to-output gain with base-to-output gain, input resistance and estimated output peak. Inspect the clipping warning and output resistance.
Settings and limits
- Emitter bypass
- Ideal bypass removes emitter degeneration for AC while retaining DC bias. It raises common-emitter gain but generally reduces input resistance; a real capacitor is frequency dependent.
- Source and load
- Source resistance attenuates the signal entering the base. The AC load affects gain and headroom; it is capacitively coupled and does not enter the DC bias calculation.
- Small-signal assumptions
- Thermal voltage and bias current determine transconductance. The clipping estimate compares predicted peak swing with available headroom; it is not a distortion simulation.
Worked example
Apply the shared divider-bias example below and compare the common-emitter results with bypass disabled and enabled. Bias stays unchanged while gain and input resistance change.
Example input
NPN; VCC = 12 V; R1 = 47 kΩ; R2 = 10 kΩ
RC = 4.7 kΩ; RE = 1 kΩ; β = 100
VBE = 0.7 V; VCE(sat) = 0.2 V; VT = 25.85 mV
RL = 10 kΩ; RS = 1 kΩ; Vin,pk = 10 mV| CE / CE+Cb / EF | Gsource | Rin | Vout,pk | Rout |
|---|---|---|---|---|
| CE | −2.744393 V/V | 7.634495 kΩ | 27.443927 mV | 4.7 kΩ |
| CE + Cb | −98.277923 V/V | 1.615793 kΩ | 982.779227 mV | 4.7 kΩ |
| EF | 0.864522 V/V | 7.579523 kΩ | 8.645220 mV | 27.924813 Ω |
Switch to emitter follower. Its voltage gain is below unity, but its lower output resistance may be useful for buffering. Collector resistance is not used in follower mode.
Questions and troubleshooting
Why is the gain negative?
A common-emitter stage inverts the signal. An emitter follower is non-inverting; compare signed voltage gain rather than only its magnitude.
Why are small-signal results missing?
Cutoff or saturation invalidates the active-region model. Correct the DC operating point before comparing AC gain.
Does a passing clipping check mean low distortion?
No. Nonlinearity exists before hard clipping. Reduce signal size and verify frequency response, bias stability and distortion for the actual circuit.